Friday, April 16, 2010

HP 1650A Logic Analyzer is Working

A bit more than a year ago, one of the generous members of SHARC gave me an old logic analyzer.  The Hewlett Packard 1650A didn't come with probes, but with some cash outlay and simple cable building I finally got the old machine back in business.

First, I needed a pod, which is a collection of probe wires bundled together to a common connector. I found one on eBay for a decent price and it came with a set of claw grabber clips, but I ordered another set of single claw clips that will work better for DIP chips.

Claw clip in upper left, DIP clips in foreground

When the pod arrived, I realized I also needed a female-female IDC ribbon cable to hook the pod to the back of the machine. Finding the original HP cable for anything less than an astronomical, outrageous price proved impossible, so I decided to build my own.  Easy enough.

Ribbon cable and IDC plugged into pod 1 (center)

A 40-pin IDC connector on each end and 40-conductor ribbon cable is required. I chose to use twisted pair ribbon cable similar to HP's cable, in hopes that this will increase noise immunity versus a plain flat ribbon. Technically the pod only has 37 pins but the connector width is designed for a 40-pin IDC. If you want to save a little time, here's a link to the list of parts on Mouser. Cost was just over $25.

Putting The Logic Analyzer to Use

So how do you use one of these things?  I found this Tektronix white paper, The XYZs of Logic Analyzers.pdf to be a helpful, quick introduction. So, I tried the thing out, with my still-in-progress Oscilloscope Calibrator project as the SUT (system under test).

Logic analyzers can display state information or timing information (some do both at once). Selecting timing waveform display, and telling the analyzer to capture and overlay multiple samples, the logic analyzer quickly identified that the clock signal coming from the 74HC04 is showing some variance (the top waveform on the screen below).

Screen shot, multiple samples accumulated

The vertical lines with X and O (detail below) are markers used to measure timing. By moving these markers around on the screen, I could figure out that the clock signal was rising as much as 20ns early and falling as much as 20ns late as shown by the double vertical rise bars on the top signal, where multiple samples are overlaid.

The waveforms below the top waveform are the frequency-divided signals that will be the output of the calibrator (coming off the 74LS393 and 74LS162). Now, I'm not crazy about 40ns of clock jitter out of a 240ns clock period, but I think that overall accuracy of the frequency is good enough for now.

Screen detail, timing variance, and markers

I'll probably try to fix it anyway to see what I can learn about the cause of the problem. Maybe it's simply a question of replacing the resonator with a crystal, or addressing noise or capacitance issues, I don't know.

Meanwhile, the logic analyzer works. So I can use it for testing and troubleshooting all sorts of digital signals. It's an old machine so I can't use it for modern high frequency CPUs but I would think it'd be more than fine for slow robot microcontrollers and certainly for slow serial and parallel communications between devices.

The only thing left was to fix the the dim CRT.  Some tweaking of an internal calibration potentiometer and fixing the rear intensity control knob and it's as bright as it will ever need to be now.

No comments:

Post a Comment

Note: Only a member of this blog may post a comment.