This is a smackdown cage match between my three logic analyzers, a vintage HP 1650A, cheap Open Workbench Logic Sniffer and tiny Saleae Logic. Who will win? Read on...
Thursday, September 12, 2013
You open up an Eagle board file only to find clearance errors when you run design rule check (DRC). Clearances that were working yesterday, and for the past hundred days on numerous boards, in fact.
Then you notice polygon isolation (clearance between polygon and trace) is too large. Pins that used to be connected to the polygon aren't. You can't manually reduce isolation. How do I fix this strange behavior?